
module ctrl_unit
#(
parameter NUM_WAY   = 4,            // NUM_WAY = 2**WAY_WIDTH,
parameter SET_WIDTH = 10,           // SET_WIDTH=ADDR_MEM_WIDTH - ADDR_CACHE_WIDTH - WAY_WIDTH,
parameter TAG_WIDTH = 11           //ADDR_MEM_WIDTH - CACHE_LINE_WIDTH - SET_WIDTH
)

//----------------------------------------------------
//IO port declarations
//----------------------------------------------------
(
    input   clk,
    input   rst,

    input   valid_arb2tag,
    output  ready_arb2tag,
    input   ready_tag2rpbuf,
    output  valid_tag2rpbuf,
    input   ready_tag2rout,
    output  valid_tag2rout,
    input   ready_tag2ftch,
    output  valid_tag2ftch,


    input   repalce_done,
    input   wr_rd,           //write or read indicator - '0' read : '1' write
    input   write_policy,    

    input   [NUM_WAY-1:0]   way_evict,
    input   [SET_WIDTH-1:0] set_rqst,
    input   [TAG_WIDTH-1:0] tag_rqst,

    input   cache_hit,   // hit flag of each way    
    input   empty_i,
    input   valid_i,
    input   dirty_i, 
    input   lock_i,

    output  en_update,
    output  empty_update,
    output  valid_update,
    output  dirty_update, 
    output  lock_update,
    output  [SET_WIDTH-1:0] set_update,
    output  [TAG_WIDTH-1:0] tag_update
);

//-----------------------------------------------------------
//           Cache line state FSM 
//-----------------------------------------------------------

endmodule 
